The "backplane problem," of course, is just one aspect of building viable, fast-to-market, robust, cheap (the euphemism is "cost effective") HA systems for the most demanding real-time communications apps.
Another aspect is that pesky, and eternally ongoing, dialogue about how to encapsulate and combine functionality within discrete components. How to provide hardware that - alternatively - can leverage practical allegiances between discrete functions (for example, the natural collaboration of portwise digital line interfaces with DSP for call progress analysis and tone generation), or serve the needs of special applications for particular kinds of function concentrations (e.g., the need of a speech-rec or high-density gateway application for "a big pool of DSPs") - all the while keeping things simple both for hardware designers and application developers.
The industry's response to these issues - and to issues limiting throughput on pure CPCI systems to around 1.3 Gbps - has been the creation of AdvancedTCA (ATCA) - the Advanced Telecomputing System Architecture, standardized as PICMG 3.0 (with decimal revs - 3.1, 3.2, etc., relating the standard to different packet backplane types: Ethernet, Infiniband, StarFabric, PCI Express, RapidIO, cPSB, and the various VITA implementations).
ATCA defines a new kind of resource board with an 8U x 280-mm form factor and 1.2 inch slot spacing, providing lots of 2D real estate, plus inter-slot headroom for "tall" CPU/sink and CPU/fan/refrigeration components. It uses a ZD backplane connector, capable of 5 Gbit/s throughput - fast enough to handle the demands of present generation gigabit-Ethernet-based packet backplane designs, as well as higher-speed architectures such as Intel and the PCI SIG's PCI Express 2.5 Gbps PCI-replacement initiative.
The standard requires dual-redundant -48VDC power, and cooling capacity of 200W per board. System management and other features are also closely specified.
