NEXT GENERATION BUSES
As computer telephony purveyors began going after bigger game - large-enterprise and telco-grade applications - weaknesses of the original PEB/ MVIP/SCSA vision became more apparent. Not only did the industry need to come to agreement on a common bus standard, but it was additionally necessary to develop a standard resource-sharing architecture for mission-critical enterprise and telco-grade applications.
As industry manufacturers finally standardized on H.100, a single telephony bus for the PCI platform, a a similar collaboration led by Performance Technologies and PICMG (the Peripheral Interface Computing Manufacturer's Group) began to develop CompactPCI, and the H.110 bus - an enhanced architecture capable of supporting hot-swap and other key features needed for mission-critical enterprise and carrier communications systems. CPCI is now the dominant overall architecture for conventionally integrated HP/HA communications platforms, and for many other mission-critical apps as well.
Initially, of course, CPCI was just a hardware/firmware specification - promising more in principle than in actuality. Making CPCI dominant has been the result of several years of effort on the part of server, backplane, single board computers (SBCs), and system manufacturers to master and standardize approaches to making CPCI's intrinsic capabilities useful - but not burdensome - to application developers.
Companies like Performance Technologies, Elma/Bustronic, Carlo Gavazzi and others have developed comprehensive libraries of backplane designs, enclosures, single-board computers, connector schemes, cooling subsystems, plus a host of monitoring, checkpointing, redundant failover and other software technologies, aimed at reducing the impact of failures on overall system availability, and the gradual elimination of single points of failure within a chassis or an extended platform.
