Those of us that follow the flash memory/SSD market have been aware for a while that the foundries were, with each shrink of their process, approaching a hard limit. The Intel-Micron and Toshiba-SanDisk flash memory ventures recently announced that they’re solving the problem by joining Samsung and taking their flash 3D.
As Gordon Moore famously observed more than 40 years ago, the number of transistors per chip doubles every two years. This has given us servers with 18 core CPU chips with half a terabyte of memory.
While we can hopefully continue to reap the benefits of shrinking geometries in our CPUs for another decade or more, conventional planar flash memory has already reached the stage where shrinking memory cells beyond their current 16nm size is no longer practical.
The problem is that today’s 16nm flash cells only hold on the order of 100 electrons. Since a triple-level cell (TLC) stores data as eight separate charge levels, the difference between one state and another is just a dozen or so electrons. Even if a cell could be shrunk to 12nm, the resulting device would be so sensitive to two or three stray electrons that it wouldn’t be very useful. At Micron’s analyst day earlier this year, company executives told us that 16nm will be their last generation of 2D, or planar, flash.
The chip foundries’ solution is to stop laying flash cells side by side like the row houses in my former hometown of Hoboken, but instead stacking cells vertically like the skyscrapers of Dubai.
Toshiba and SanDisk said they’re sampling a 128 GB chip that stacks flash cells 48 high while IMFT (the Intel/Micron venture) almost simultaneously announced sampling of a 32-layer chip storing 256 GB. As part of the announcement, Micron suggested that the density of thesechips would allow vendors to pack 10 TB of capacity in the common 2.5” SSD package.
With these announcements, both ventures join Samsung, which has been shipping 3D TLC chips in its SSDs since last summer. Some industry analysts have speculated that Samsung was using its 3D flash exclusivly in its own SSDs, as opposed to selling the chips on the open market, as a way to optimize the process even as itsproduction costs for 3D flash were higher than its competitors' costs for planar flash.
As my friend and noted semiconductor analyst Jim Handy said on a recent episode of the Greybeards on Storage podcast, adding layers to a flash chip involves depositing many layers of materials on the silicon chip substrate and then etching a series of holes, into which the flash cell chains can be insterted. Since the expensive etching and lithography stages don’t have to be repeated for each layer, per chip costs remain roughly the same as bit density increases.
The transition to 3D will require the chip foundries to develop new processes and interestingly, each is using a different approach. Toshiba/SanDisk uses their BiCS (Bit Cost Scaling), therefore joining Samsung in using charge-trap technology, while IMFT’s 3D tech sticks with the floating-gate technology used in planar flash.
All the 3D flash chips use significantly larger geomitries than today’s planar flash. IMFT’s 32-layer chip has roughly twice the bit density of its 16nm planar flash, which would imply a cell size of roughly 60nm. While Micron is only claiming the same 3,000 program/erase cycle endurance as for its planar chips, that’s almost certianly a marketing decision.
All that space means more electrons per cell and as 3D technology matures, vendors should be able to deliver TLC devices with the endurance of today’s planar multi-level cell (MLC). We can expect future generations of 3D flash to boost bit density by shrinking geometries as the vendors figure out how to etch ever smaller holes, and more layers.
While the fourth flash vendor, South Korea’s SK Hynix, hasn’t yet announced a 3D chip, the future of flash -- like Manhattan real estate -- is definitely looking up. The designers of next generation non-volitile memories like PCM and MRAM will have to compete with ever denser flash for at least another few years.
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