"This architecture is a big breakthrough for us," said Dave Donatelli, EMC's EVP of platform operations, at the launch in New York this week. "We've removed the major bottleneck -- the internal bandwidth of the system."
Competitors, though, dispute that the DMX really offers substantially better performance. "Their claims of performance is adding up the sum of the parts," said Phil Townsend, HDS's senior director of product marketing. They say the more relevant figure -- and the real architectural bottleneck -- is that the cache memory access on DMX is 16 GByte/s (32 cache segments multiplied by 500 MByte/s for each interface).
Fine, says EMC: The DMX still whomps the tar out of the nearest competitor. Its 16-GByte/s cache bandwidth is still well over the 10.6-GByte/s cache bandwidth Hitachi claims for the 9980V (four cache regions times 2.65 GByte/s provided by the Hi-Star crossbar switching architecture).
Table 1: High-End Storage Performance Specifications
| Hitachi Lightning 9970V | EMC Symmetrix DMX1000 | Hitachi Lightning 9980V | EMC Symmetrix DMX2000 | |
| Data Bandwidth | 16 x 332 MB/s = 5.3 GB/s | 64 x 500 MB/s = 32 GB/s | 32 x 332 MB/s = 10.6 GB/s | 128 x 500 MB/s = 64 GB/s |
| Message Bandwidth | 16 x 166 MB/s = 2.6 GB/s | 16 x 200 MB/s = 3.2 GB/s | 32 x 166 MB/s = 5.3 GB/s | 32 x 200 MB/s = 6.4 GB/s |
| Cache Regions | 2 | 16 | 4 | 32 |
| Cache Bandwidth | 2 x 2.65 GB/s = 5.3 GB/s | 16 x 500 MB/s = 8 GB/s | 4 x 2.65 GB/s = 10.6 GB/s | 32 x 500 MB/s = 16 GB/s |
| Cache Size | 32 GB | 64 GB | 64 GB | 128 GB |
| Front-End Connectivity | 48 2-Gbit/s FC | 48 2-Gbit/s FC | 64 2-Gbit/s FC | 96 2-Gbit/s FC |
| Processors | 8 166MHz MIPS 8 200MHz MIPS |
60 500MHz PowerPC | 16 166MHz MIPS 16 200MHz MIPS |
116 500MHz PowerPC |
| Source: EMC, HDS | ||||
Apart from this circular they-said/we-said quarrel, EMC's rivals bellyache that Hopkinton can't prove the DMX delivers superior performance, because EMC refuses to test its systems using industry-standard benchmarks.
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